Kadence Electronics (Cadence, USA) announced today that SGS-TüV Saar has independently certified that the Cadence Tensilica Xtensa processor with FlexLock function meets the ISO 26262:2018 standard and reaches the ASIL-D level, which is the highest automotive safety integrity level rating. level. The functional safety certification covers everything from basic microcontrollers to high-performance DSPs. They all have FlexLock configuration options, provide stronger random failure protection, and follow a robust safety process development to prevent system failures. The Tensilica Xtensa processor with FlexLock function is very suitable for the automotive market, tailored for artificial intelligence, vision, radar, lidar, audio, car networking (V2X) and control applications.
“Cadence Tensilica FlexLock processors are optimized for automotive applications and are the industry’s first processors that fully comply with ASIL-D functional safety standards.” said Wolfgang Ruf, director of functional safety of SGS-TüV Saar Semiconductor, “according to ISO 26262:2018 Standard ASIL-D system and random failure avoidance comprehensive evaluation certification proves that Cadence IP has reached a very high level of functional safety quality. System-level chip designers can safely adopt and apply Tensilica processor IP design that has obtained functional safety certification , Which can meet the stringent safety-critical requirements of the automotive industry.”
The key to ASIL-D compliance is the new FlexLock feature, which adds support for lockstep to the flexible and extensible Xtensa processor architecture. Lockstep is a proven method that improves the security of software execution by providing core logic redundancy at the hardware level. Not only does it provide the support needed to obtain ASIL-D certification, but FlexLock also brings the design team the ability to run two processors independently in an ASIL-B solution. In addition, the FlexLock solution allows local memory and two processor caches to be run in lockstep mode, achieving a higher level of memory failure protection.
“In meeting the emerging trends and needs of the automotive industry, the innovation of functional safety features will still be the key.” said Robert Dunnigan, project manager of NXP’s ADAS MCU project. “We are very pleased to see that Cadence is adding significant Functional safety mechanisms, such as the FlexLock dual-core lockstep function.”
“The current trend in the automotive industry requires a higher level of functional safety.” said Liu Hongquan, senior marketing director of Calterah. “The addition of FlexLock dual-core lockstep function can meet the most critical functional safety requirements. This is Cadence’s commitment A strong proof of meeting customer needs.”
“Higher autonomous driving capabilities require a higher level of intelligent computing at the edge of the automotive application field, which drives the demand for higher levels of functional safety.” said Larry Przywara, senior group director of Tensilica’s market at Cadence. “With With the introduction of the FlexLock function, users of Tensilica controllers and DSPs can obtain the highest level of ASIL-D certification, as well as the random hardware failure protection it brings. Choose Tensilica IP to speed up ADAS, radar, lidar, V2X and vision processing Speed design engineers can be confident that they can meet customer requirements for functional safety.”
Like other Xtensa processors, ASIL-D-certified cores can be customized using the Tensilica instruction extension (TIE) language to optimize IP for specific applications, with the appropriate performance level and the highest level of security. The Tensilica Xtensa processor with FlexLock function is now on the market, enabling excellent system-level chip design and supporting Cadence’s Intelligent System Design (Intelligent System Design?) strategy.